The present invention generally relates to partial reconfiguration of programmable logic devices.
Programmable logic devices (PLDS), such as field programmable gate arrays (FPGAs), are increasingly being used in applications where ASICs have traditionally been used, and in other applications to supplement the capabilities of microprocessors.
Some FPGAS, such as the Virtex-II FPGA from Xilinx, Inc., support partial reconfiguration. That is, once configured, selected resources of the FPGA can be reconfigured without having to reconfigure the entire device. Partial reconfiguration has often been performed under software control. For example, the JBits environment from Xilinx supports software-controlled full and partial reconfiguration of an FPGA.
Software-controlled reconfiguration provides flexibility in developing a reconfiguration controller that meets application-specific requirements. However, software-controlled reconfiguration may be too slow for certain applications. The latency associated with execution of the program code that controls the reconfiguration may be too slow for some application requirements.
A system and method that address the aforementioned problems, as well as other related problems, are therefore desirable.
The present invention provides a circuit arrangement for partial reconfiguration of a programmable logic device (PLD). In one embodiment, a modification table is configured with addresses and associated data values for implementing desired changes in the configuration. A configuration store stores a copy of the configuration store of the PLD. Each address in the modification store references an address in the configuration store, and each associated data value indicates a configuration state for that address. The configuration store may store configuration data for all or a selected subset of the reconfigurable resources of the PLD. A controller is coupled to the modification and configuration stores and to the PLD. In response to a reconfiguration signal, the controller reads an address and associated data value from the modification store, updates the configuration store at the address read from the modification store with the associated data value, and subsequently downloads configuration data from the configuration store to the PLD.
The modification store may include data and addresses for every value in the configuration store that can be changed, or if the PLD is implementing a highly repetitive function, the modification store can store a repetitive unit of configuration changes, and the controller can determine where in the configuration store to make the changes specified by the repetitive unit.
Various other embodiments are set forth in the Detailed Description and Claims which follow.